Thus, the particular embodiments disclosed above are illustrative only and should not be taken as limitations upon the present invention, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Structure and method to reduce polysilicon loss from flash memory devices during replacement gate RPG process in integrated circuits. ALD, or any combination s thereof to a thickness of approximately Angstroms, though a thinner or thicker layer may also be used. Any remaining unetched portions of the patterned mask or photoresist layer s are stripped. In the planarized dielectric layerspatterned openings are formed e. On the gate dielectric layersthe patterned conductor layers and may be formed, such as by depositing a first barrier metal layer over the gate dielectric layers and then blanket-depositing a layer of polysilicon or SiGe over the barrier metal layer by CVD, PECVD, PVD, ALD, or any combination s thereof to a predetermined thickness. For example, the second planarized dielectric layer may be formed by depositing a conformal layer or film of silicon oxide which is then polished to a flat or planarized surface which exposes at least the upper portions of the sacrificial CMOS gate electrode devices. In selected example embodiments, the planarized dielectric layer may be formed as part of a first interlayer dielectric layer or stack by depositing and polishing a dielectric layer to have a predetermined thickness. In selected embodiments, the sacrificial transistor gate structures may be formed by depositing one or more high-k dielectric layers over the elevated substrate using a dielectric material which has a dielectric constant value of 7.
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as well as other III/V or II/VI compound semiconductors or any combination thereof.
form the split-gate electrodes in the flash memory cell device region. . may include an element selected from the group consisting of Ti, Ta, La, Ir, USB2 Samsung Electronics Co., Ltd.
The semiconductor fabrication process of claim 1where forming the plurality of nonvolatile memory cell gate structures comprises forming a plurality of split-gate bitcells, each comprising a polished and recessed control gate formed adjacent to a charge storage layer comprising a plurality of discrete storage elements, where the charge storage layer separates the polished and recessed control gate from an adjacent polysilicon select gate.
As will be appreciated, any desired gate patterning and etch sequence may be used to form the patterned gate electrode stacks, including but not limited to photoresist or a hard mask formation, TEOS etch using the photoresist as a maskARC etch using the remnant TEOS as a maskpre-etch cleaning, oxide break through, main poly plasma etch, soft landing etch, poly clean overetch, and post-etch cleaning. By using a timed CMP process, the planarized dielectric layer exposes or partially removes the top of the sacrificial gate electrode.
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As deposited, the dielectric layer can be planarized to form the planarized dielectric layer salone or in combination with other dielectric layers, such as one or more gettering dielectric layers e. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements. By selectively forming the epitaxial semiconductor layer from the underlying substrate layers, the semiconductor layer has the same crystallographic orientation as the silicon substrate layers
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